The present invention, in some embodiments thereof, relates to a gain cell with internal feedback and, more particularly, but not exclusively, to a four-transistor gain cell with internal feedback.
Modern microprocessors and other VLSI systems-on-chip (SoCs) implemented in aggressively scaled CMOS technologies are characterized by high leakage currents, and require an increasing amount of embedded memory [ref. 1]. Such embedded memory, typically implemented as 6-transistor (6T)-bitcell SRAM macrocells, not only consume an ever growing share of the total silicon area but also significantly contributes to the leakage power of the system. (The leakage power is a large share of the total power budget in deeply scaled CMOS nodes.) Unfortunately, besides several advantages like fast access speed and robust, static data retention, the 6T SRAM bitcell is relatively large, exhibits several leakage paths, and has dramatically increased failure rates under voltage scaling.
Gain-Cell embedded DRAM (GC-eDRAM) [refs. 2-5] circumvents the limitations of SRAM while remaining fully compatible with standard digital CMOS technologies. Furthermore, GC-eDRAMs exhibit low static leakage currents, are suitable for 2-port memory implementations, and provide non-ratioed circuit operation. The main drawback of GC-eDRAMs is the need for periodic, power-hungry refresh cycles to ensure data retention.
The Data Retention Time (DRT) of GC-eDRAMs is the maximum time interval from writing a data level into the bitcell to still being able to correctly read out the written level. The DRT is primarily limited by the level set by the initial charge stored in the bitcell and the leakage currents that degrade this level. Gain cell implementations in mature technology nodes, such as 180 nm, have been shown to exhibit high DRTs of tens to hundreds of milliseconds [ref. 4,5]. However conventional 2T gain cells in newer technology nodes, such as 65 nm, display much lower DRTs of only tens of microseconds [ref. 6]. The lower DRT is a direct consequence of the substantially higher leakage currents which result in a much faster deterioration of the stored levels [ref. 5]. Depending on the type of write transistor (WT), one of the data levels has a much higher retention time than the other (e.g. data ‘1’ for a PMOS WT and data ‘0’ for a NMOS WT) [ref. 6]. However, when determining the refresh frequency, one must consider the deterioration of the weaker data level under worst-case conditions, i.e. when the write bitline (WBL) is driven to the opposite level of the stored data during retention periods.